Machine vision (MV) is an important tool in Industry 4.0, autonomous driving, and other advanced technologies. Various standard data connectors and application-specific vision system connectors support it. MV hardware consists of a camera or other imaging sensor and a computer that analyzes the images. Reliable, high-speed connectivity is required to link them. Examples of standard […]
How do car camera bus and FPD Link compare?
Car camera bus (C2B) and flat panel display (FPD) Link are both technologies used in automotive vision systems, but they differ in their use cases, performance, and cost. Automotive high-definition link (AHL) is another choice for video connectivity, as is automotive Ethernet, a general-purpose networking technology. This article briefly compares FPD Link, C2B, and AHL. […]
How twin axial cable assemblies support high-performance computing for AI/ML systems
The high-performance computing platforms used for artificial intelligence (AI) and machine learning (ML) in hyperscale data centers need high-speed interconnects like 112 Gbps PAM 4 and faster inside the servers. High-speed interconnects are also required between the servers and storage devices. Twin axial (Twinax) cable assemblies are one way to address those needs. This article […]
What specifications are needed for card edge connectors in AI/ML systems?
Card edge connectors connect peripheral devices or expansion cards to a host system. They provide a reliable interface for data transfer and power delivery, facilitating the integration of artificial intelligence (AI) components into a system. They support AI and machine learning (ML) on the edge, in the cloud, and in hyperscale data centers. This article […]
How do 224 G connectors support AI/ML training in hyperscale data centers?
224 Gigabits per second (Gbps) pulse-amplitude modulation 4-level (PAM 4) technology is foundational for the hyperscale data centers needed for artificial intelligence (AI) and machine learning (ML) training and implementation. This article begins by examining the multiple uses of 224 G connectivity in servers and storage devices. It then considers how multiple 224 G lanes […]
What interconnects are used with memory for HPC and AI?
High-performance computing (HPC) for artificial intelligence (AI) applications places extreme demands on memory connectors. They must deliver high-speed connectivity, high levels of signal integrity (SI), and support high-density solutions. This article reviews connector needs for Peripheral Component Interconnect Express 6.0 (PCIe 6.0), Serial Attached SCSI (SAS) including SAS 3.0, 4.0 and SAS/PCIe 5.0, and Data […]
How are high-speed board-to-board connectors used in ML and AI systems?
High-speed board-to-board connectivity is evolving to meet the increasing performance demands and need for scalability of machine learning (ML) and artificial intelligence (AI) systems. The basic PCIe connectors and Card Electromechanical (CEM) form factor are still widely used to support scalability and high performance, but there are also new contenders. This article reviews the basics […]
What multidrop SPE architectures are there to choose from?
The IEEE 802.3 single-pair Ethernet (SPE) standards include multidrop and daisy-chain architectures that support applications like automotive, industrial, and smart buildings. In addition, a range of SPE connector standards are available with several environmental classifications and ratings based on mechanical, ingress, climatic/chemical, and electromagnetic (M.I.C.E) attributes. Automotive systems are a key target for SPE deployment. […]
What are the performance requirements for multidrop SPE connectivity?
Specifications are provided for the insertion loss, return loss, and mode conversion loss in the link and mixing segments of a Single-Pair Ethernet (SPE) network. Connector specifications are also provided for coupling attenuation, impedance, return loss, and dielectric strength. This article begins by briefly examining where multidrop fits in the range of Ethernet connectivity options. […]
What are the PHY implementations of multidrop SPE?
There are three common physical layer (PHY) variants for multidrop Single-Pair Ethernet (SPE), basic PHY, media access controller (MAC) PHY, and transceiver. They rely on different interfaces, including a media-independent interface (MII), reduced media-independent interface (RMII), serial peripheral interface (SPI), OPEN Alliance 3-pin (OA-3P), and Ethernet advanced physical layer (Ethernet-APL). This article begins with a […]
