• Skip to primary navigation
  • Skip to main content
  • Skip to primary sidebar
  • Skip to footer
  • Advertise
  • Subscribe

Connector Tips

Connector Tips has connector and electrical connector news, product highlights and and editorial coverage.

  • Products
    • board-to-board
    • cable-to-board
    • power
    • RF
    • USB
    • wire-to-board
  • Electronics
    • bonding
    • copper
    • fiber
    • gold
    • optical
    • transistor sockets
  • Markets
    • Aerospace
    • Automation
    • Automotive
    • Electrification
    • Electrical & Instrumentation
    • Medical
    • Military
    • Off-Highway
    • Oil/Gas
    • Telecom/Data
  • Learn
    • Basics/FAQs
    • eBooks/Tech Tips
    • EE Training Days
    • EE Learning Center
    • Tech Toolboxes
    • Webinars & Digital Events
  • Resources
    • Design Guide Library
    • Digital Issues
    • Engineering Diversity & Inclusion
    • LEAP Awards
    • White Papers
    • DesignFast
  • Videos
    • EE Videos
    • Teardown Videos
  • Newsletter Subscription
  • Suppliers

Intelligent interconnect optimizes AI data transmission with DSP-free design

September 17, 2024 By Redding Traiger Leave a Comment

TeraSignal introduced TSLink, the world’s first intelligent chip-to-module (C2M) interconnect designed to revolutionize data transmission between large ASICs and linear optical modules. Leveraging existing microcontroller resources in optical modules, the TSLink solution automates link training and performance monitoring without the need for additional digital signal processors (DSPs). TSLink dramatically reduces power consumption and latency while simplifying deployment, enabling a true plug-and-play linear optics solution for AI and high-performance computing.

TSLink leverages the DSP-based SerDes functionality already present in AI ASICs and GPUs, providing a streamlined connection that optimizes performance across various protocols and modulation schemes. This architectural innovation, enabled by TeraSignal’s TS8401/02 Intelligent Re-Drivers, positions the company at the forefront of interconnect technology by offering a highly adaptable and energy-efficient solution for next-generation AI infrastructure.

TSLink can interface seamlessly with existing ASICs and simplifies the process of connecting ASICs to various types of linear optics such as linear pluggable optics (LPO), near package optics (NPO), co-packaged optics (CPO), and active copper cables (ACC). This plug-and-play capability streamlines and simplifies deployment, reducing the complexity typically associated with traditional high-speed interconnects. Designed to be agnostic to leading protocols (Ethernet, PCIe, InfiniBand, etc.), modulation schemes (NRZ, PAM4, etc.), and media (fiber, copper), TSLink offers exceptional flexibility across different applications, making it a highly adaptable solution for various data transmission needs.

Traditional interconnects rely on DSPs to manage data transmission, leading to increased power consumption and latency. TSLink eliminates these bottlenecks by embedding advanced discrete-time signal processing algorithms directly into the interconnect, intelligently managing data transmission and ensuring optimal link integrity without the need for redundant digital signal processing.

Key TSLink Benefits include: Automatic Link Training: By leveraging the Common Management Interface Specification (CMIS), TSLink automatically characterizes the host to module channel and provides the optimum settings for the DSP-based transmitter in the host; Link Diagnostics and Monitoring: TSLink includes features like digital eye monitoring and bit error rate (BER) reporting, allowing users to easily monitor channel conditions and ensure optimal performance in the link; Reduced Power Consumption: By using existing microcontroller resources and eliminating the need for additional DSPs, TSLink reduces power consumption by at least 50%, making it a more sustainable solution for high-density AI deployments. Lower Bit Error Rate: TSLink eliminates the quantization noise introduced by analog-to-digital converters (ADCs) in DSP-based re-timers, significantly improving the BER in the link.; Reduced Latency: TSLink removes the high latency caused by DSP processing, enabling shorter transmission time, which is critical for high-performance, compute-intensive AI applications.; Improved Signal Integrity: The advanced link training process shapes the transmit signal based on the characteristics of each individual channel, ensuring maximum signal to noise ratio at the receiver; Small Form Factor: Eliminating the need for DSPs results in at least a 50% reduction in silicon die size, contributing to lower production costs and higher density linear optics.

TSLink uses advanced impulse response link training (IRLT) to accurately characterize and compensate for channel impairments, such as inter-symbol interference (ISI), reflection, and crosstalk. By embedding this intelligent link training directly into the interconnect, TSLink ensures high signal integrity with reduced bit error rates, while minimizing power consumption and eliminating the need for DSPs in the optical module. This protocol-agnostic approach provides flexibility across various high-speed serial protocols, making TSLink an adaptable solution for next-generation AI-centric data centers and high-performance computing environments.

TeraSignal is now offering TSLink reference designs, complete with TSLink firmware and the TS8401/02 Intelligent Re-Driver, to select partners and customers. Broader TSLink reference design availability is expected later this year.

You may also like:


  • What specifications are needed for card edge connectors in AI/ML…

  • How do 224 G connectors support AI/ML training in hyperscale…

  • What interconnects are used with memory for HPC and AI?

  • How are high-speed board-to-board connectors used in ML and AI…

  • What multidrop SPE architectures are there to choose from?

Filed Under: AI/ML, connector components, Products, RF Tagged With: terasignal

Reader Interactions

Leave a Reply Cancel reply

You must be logged in to post a comment.

Primary Sidebar

Featured Contributions

From extreme to mainstream: how industrial connectors are evolving to meet today’s harsh demands

The case for vehicle 48 V power systems

SMP3 vs. SMPS: why two standards?

mmWaves bring interconnect challenges to 5G and 6G

Ensuring integrity in high-performance interconnects with connector backshells

More Featured Contributions

EE TECH TOOLBOX

“ee
Tech Toolbox: Internet of Things
Explore practical strategies for minimizing attack surfaces, managing memory efficiently, and securing firmware. Download now to ensure your IoT implementations remain secure, efficient, and future-ready.

EE LEARNING CENTER

EE Learning Center

RSS Current EDABoard.com discussions

  • Why does Synopsys DC need Inverters and Buffers if my RTL only has XOR logic?
  • I/O constraint for Hold check
  • SPI speed pic18f66j15
  • GanFet power switch starts burning after 20 sec
  • RF-DC rectifier impedance matching

RSS Current Electro-Tech-Online.com Discussions

  • LED circuit for 1/6 scale diorama
  • stud mount Schottky diodes
  • Hi Guys
  • using a RTC in SF basic
  • Can I use this charger in every country?

EE ENGINEERING TRAINING DAYS

engineering
“bills
“connector
EXPAND YOUR KNOWLEDGE AND STAY CONNECTED
Get the latest info on technologies, tools and strategies for EE professionals.

Footer

EE WORLD ONLINE NETWORK

  • 5G Technology World
  • EE World Online
  • Engineers Garage
  • Analog IC Tips
  • Battery Power Tips
  • DesignFast
  • EDA Board Forums
  • Electro Tech Online Forums
  • EV Engineering
  • Microcontroller Tips
  • Sensor Tips
  • Test and Measurement Tips

Connector Tips

  • Subscribe to our newsletter
  • Advertise with us
  • Contact us
  • About us

Copyright © 2025 · WTWH Media LLC and its licensors. All rights reserved.
The material on this site may not be reproduced, distributed, transmitted, cached or otherwise used, except with the prior written permission of WTWH Media.

Privacy Policy