What is multidrop SPE?

There are three common physical layer (PHY) variants for multidrop Single-Pair Ethernet (SPE), basic PHY, media access controller (MAC) PHY, and transceiver. They rely on different interfaces, including a media-independent interface (MII), reduced media-independent interface (RMII), serial peripheral interface (SPI), OPEN Alliance 3-pin (OA-3P), and Ethernet advanced physical layer (Ethernet-APL).

This article begins with a brief review of point-to-point (P2P) and multidrop, looks at the three multidrop SPE PHY variants, and then explores some of the details of the various interfaces.

In a P2P architecture, the communication channel is a dedicated link between two devices. There is generally a one-to-one correspondence between transmitter channels and receivers. In a multidrop architecture, the channel is shared among multiple devices or nodes, there is one transmitter and multiple receivers.

PHY implementations for multidrop SPE

PHY is used across all types of Ethernet-based systems, including multidrop. In this implementation, the PHY and MAC are separated. The PHY in the node includes functions like coding, arbitration, cable driver, and so on. The MAC is in the MCU and is connected to the PHY using MII or RMII.

MAC-PHY includes both the MAC and PHY elements in the node that’s connected to the MCU using an SPI interface.

Transceiver-based devices move both the MAC and PHY into the MCU. This implementation was originally developed for automotive applications defined in 802.3cg 10BASE-T1S (short range) using AO-3P and for industrial applications defined in 802.3cg 10BASE-T1L (long range) using Ethernet-APL.

Figure 1. PHY (left) is common across many Ethernet systems, including multidrop, MAC-PHY (center) is used across various multidrop architectures, and transceiver (right) is used primarily with 10BASE-T1S and 10BASE-T1L multidrop systems. (Image: *Microchip*)

MII is defined in 802.3u and was originally intended for use with Fast Ethernet (100 Mbps). Media independence means that various types of PHY devices, like twisted pairs and optical fibers, can be used without replacing the MAC hardware. In addition, MII can connect a MAC to an external PHY with a pluggable connector or directly with a PHY IC on the same circuit board.

As the name states, RMII reduces the number of signals required to connect a PHY and a MAC. RMII uses about half the number of signals compared to MII, simplifying designs and reducing costs. It’s optimized for use with MCUs with an integrated MAC. Among the signal reductions is relacing separate transmit and receive clocks with a single clock. Increasing the clock frequency from 25 MHz to 50 MHz, enabling the data paths to be reduced from 4 bits to 2 bits. Multiplexing the received data valid and carrier sense signals on a single signal and removing the collision detect signal.

Compared with the 16 or 18 pins needed to implement MII and 8 pins for RMII, SPI requires only 5 pins. SPI is used with MAC-PHY integrated solutions. It reduces the demands on the MCU and enables the use of lower-power processors. This architecture is intended to support ultra-low power solutions for 10BASE-T1L industrial multidrop networks and for smart building systems like access control, elevators, security cameras, fire safety, and heating, ventilation, and air conditioning (HVAC).

AO-3P uses a three-wire transceiver interface for minimum pin count. It was developed to reduce solution weight and cost with 10BASE-T1S in automotive applications.

Ethernet APL is different

Ethernet APL is a PHY developed for use with 10BASE-T1L in long-reach industrial networks. It’s enhanced for use in applications that require intrinsic safety and includes port profiles for optional power supply and hazardous area protection. It can be implemented with a MAC or MAC-PHY interface.

For example, in Industrial Internet of Things (IIoT) applications that use low-power processors without an integrated MAC, Ethernet APL is implemented with a MAC-PHY interface that includes both the MAC and PHY elements in the node and is connected to the MCU using an SPI interface. Optionally, it can be implemented with a PHY interface where the MAC is in the MCU and is connected to the PHY using MII or RMII (Figure 2).

Figure 2. Example of Ethernet-APL field-level device data connectivity with a 10BASE-T1L PHY. (Image: *Analog Devices*)

Summary

Several PHY implementations are used for multidrop SPE. They are optimized for specific hardware designs and require a range of pin counts, from up to 18 pins for MII to 8 pins for RMII, 5 pins for SPI, and only 3 pins for AO-3P. In addition, Ethernet APL has been defined for challenging industrial applications and can use a variety of interfaces depending on whether it’s implemented with PHY or MAC-PHY.